Intel has been preparing the launch of Xe HP for many months, including basic work around their discrete graphics / accelerator support for their Linux graphics driver stack, which was a long time ago. On the Xe-HP front, an important patch series was published for the first time on Friday afternoon: first work on multi-tile support.
Intel Xe HP / Ponte Vecchio introduces the concept of a multi-tile / chiplet design. So far, the Intel Linux graphics driver has only been built around a single-tile design, but the patches sent out Friday afternoon begin with the infrastructure changes in the i915 kernel DRM driver to support multiple tiles.
The patch cover lever summarized the current state of affairs:
Some of our upcoming platforms, including Xe_HP SDV, will support a “multi-tile” design. A multi-tile platform is effectively a platform with multiple GT instances and local storage areas, all behind a single PCI device. From the i915 perspective this means several intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but more work (especially on local storage) is needed to fully enable a multi-tile platform.
Note that the presence of multiple GTs is largely transparent to the user area. A multi-tile platform will offer userspace a larger list of engines, but the concept of “tile” is not something that userspace has to deal with directly. There will be some uapi implications later as the devices have multiple local storage areas, but this aspect of Multi-Tile is not covered by this patch series and will come up in future work.
That initial basket of multi-tile code is now pending review. Given that there is more work to be done around the handling of local storage, it is unlikely that this will be buttoned in time for the next 5.16 cycle.